Complex programmable logic devices (CPLDS) use programmable AND arrays and macrocells to form sum-of-product representations of logical functions desired by a user. In addition to performing a desired logical function, users of CPLDs may also require memory functions in applications such as ATM cell processing, clock domain buffering, shift registers, finite impulse filter delay lines, or program memory. The amount of memory a user will require depends upon the particular application—some require more memory storage and others require less. Thus, it is desirable to provide CPLDs with a flexible memory capability to satisfy the majority of users.
To meet the need for a CPLD having a memory capability configurable according to an individual users needs, co-owned U.S. Ser. No. 10/133,016, (the '016 application) filed Apr. 26, 2002, discloses a programmable logic device having logic blocks that may be reconfigured to perform memory functions. In general, the programmable AND arrays within a CPLD includes fuse points that control whether input signals affect the product term outputs. Each fuse point is controlled by a memory cell whose state determines whether the corresponding input signal affects a product term output. As disclosed in the '016 application, the fuse points within a programmable AND array may be configured for use as a memory array. The '016 application is hereby incorporated by reference in its entirety.
Despite the advantageous flexible memory capability disclosed by the '016 application, certain needs in the art remain. For example, the routing structure in programmable logic devices is typically fixed during operation of the device. In other words, after the device has been configured, the routing supplied by the routing structure remains unchanged. For example, should the routing structure be configured according to the contents of a configuration memory, these contents are not changed during operation and thus the configuration of the routing structure cannot be dynamically reorganized during this time. A memory block in such a programmable logic device will thus receive data words from a fixed source during operation. For example, the routing structure may be configured to provide data words from a first logic block to a memory block. During operation, it would not be possible to change this routing such that the memory block receives data words from a second source.
Accordingly, there is a need in the art for an improved programmable device architecture providing flexible memory and routing capability.